fix: preserve riscv trap pc - #2384
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Signed-off-by: Jvle <keke.oerv@isrc.iscas.ac.cn>
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I closed #2400 in favor of this PR. One part from it is still useful. For instruction, load, and store address faults, RISC-V places the faulting address in I split the fix into a commit based directly on this PR: It does not change this PR's PC handling. I built it with |
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Hello @wtdcode. #2400 was closed in favor of this PR, @Kreijstal extracted the remaining change into c3cb167. I have verified that it applies cleanly on top of this branch. If you think this PR is suitable, I will :> |
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This PR fixes RISC-V exception PC handling in interrupt hooks.
Previously, Unicorn unconditionally advanced the RISC-V PC by 4 before invoking
UC_HOOK_INTR. That behavior was added to solveecallresume problem reported in #1477, but it also made interrupt hooks observe the wrong PC for other exceptions, as reported in #1990.This change preserves the faulting instruction address while the interrupt hook is running, and only advances PC to the saved next PC after a handled RISC-V
ecall.Note:
ebreakwill follow theUC_ERR_INSN_INVALIDpath is not affected by this change.